1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device having a nonvolatile memory (FeRAM: Ferroelectric Random Access Memory) that employs a ferroelectric material as a capacitor dielectric film.
2. Description of the Related Art
With the progress in size reduction and higher performance of the electronic equipment in recent years, the higher integration is required for the semiconductor devices mounted in such equipment. The semiconductor device having FeRAM is one of such semiconductor devices, for which the shrieked cell area is required.
Conventional method of manufacturing the FeRAM will be explained with reference to FIGS. 1A to 1C and FIG. 2 hereunder.
First, steps required to obtain the sectional structure shown in FIG. 1A will be explained hereunder. In order to get this structure, an device isolation insulating film 2 and a p-well 3 are formed on a silicon substrate 1, and then a MOSFET is fabricated on the p-well 3 by the well-known method. The MOSFET is constructed by n-type impurity diffusion regions 4a, 4b serving as the source/drain regions, conductor patterns made of titanium silicide (TiSi) layers 8a, 8b formed on surface layers of the n-type impurity diffusion regions 4a, 4b respectively, a gate insulating film 5, a gate electrode 6, sidewall insulating films 9 formed on both side of the gate electrode 6, etc. Then, a cover insulating film 7 made of silicon oxide nitride (SiON) is formed to cover the MOSFET, and a first insulating film 10 made of silicon oxide (SiO2) is formed thereon.
Formed on the first insulating film is a capacitor Q, which is constructed by sequentially laminating a capacitor lower electrode 11a, a capacitor dielectric film 12a, and a capacitor upper electrode 13a. 
Out of them, the property of the capacitor dielectric film 12a deteriorates when the film 12a is exposed to hydrogen, which has reducing property and is contained in the process troposphere for forming an insulating film over the film 12a. 
In order to prevent this deterioration, the capacitor Q is usually covered with a metal oxide film such as an alumina (Al2O3) film 14, or the like to prevent the entering of the hydrogen into the capacitor Q. The structure for protecting the capacitor Q by the metal oxide film is disclosed in Patent Application Publication (KOKAI) 2001-44375, Patent Application Publication (KOKAI) Hei 6-290984, Patent No.3056973.
Then, a second insulating film 15 made of silicon oxide is formed on the alumina film 14. Then, resist 25 is formed thereon, and hole forming windows 25a, 25b are formed by patterning the resist 25.
Then, as shown in FIG. 1B, the second insulating film 15, the alumina film 14, and the first insulating film 10 are etched in one step by the RIE (Reactive Ion Etching) while using the resist 25 as an etching mask and using the cover insulating film 7 as an etching stopper film. Thus, holes 15a, 14a, 10a are formed in above films respectively. In the following, such a etching step is called as the first etching step.
Then, as shown in FIG. 1C, the etching gas is changed, and then the cover insulating film 7 is etched by the RIE while using the resist 25 as the etching gas. Thus, holes 7a are formed in the cover insulating film 7, so that contact holes 18a, 18b each consisting of the holes 15a, 14a, 10a, 7a are formed. This etching step is called the second etching step in the following.
Meanwhile, it is preferable in the above second etching step that the sufficiently large selective etching ratio of the cover insulating film 7 to the titanium silicide layers 8a, 8b be ensured, so that the etching can be stopped on surfaces of the titanium silicide layers 8a, 8b. 
However, the above etching method cannot ensure the sufficiently large selective etching ratio, and thus the etching of the titanium silicide layer 8a is caused, as shown in a circle of FIG. 1C. In the extreme case, as shown in FIG. 2, the titanium silicide layer 8a is perfectly removed by the etching.
When the titanium silicide layers 8a, 8b are etched in this manner, contact resistances between conductive plugs (not shown), which are buried in the contact holes 18a, 18b later, and the titanium silicide layers 8a, 8b are not stabilized. Therefore, such a disadvantage is caused that values of the contact resistance are varied by respective conductive plugs.